This invention relates to a three stage router for broadcast application.
A rectangular crosspoint switch matrix is nonblocking with respect to broadcast connections, in that for any existing connection of an ith input to a set of outputs {j}, it is possible to connect the kth input to a set of outputs {1} (1xe2x89xa0j) without being blocked by the connection from the ith input to the set of outputs {j}.
The conventional three-stage router having M input terminals and N output terminals comprises a first or input stage composed of M/m router modules each having m inputs connected to respective input terminals of the router and a crosspoint switch matrix for connecting any one of the inputs of the module to any selected one of m+nxe2x88x921 outputs of the module, a second stage, or interstage, composed of m+nxe2x88x921 router modules each having M/m inputs connected each to one output of one module of the first stage and a crosspoint switch matrix for connecting any one of the inputs of the module to any selected one of N/n outputs of the module, and a third or output stage composed of N/n router modules each having m+nxe2x88x921 inputs connected each to one output of one module of the second stage and a crosspoint switch matrix for connecting any one of the inputs of the module to any selected one of n outputs of the module, connected to respective output terminals of the router.
It has been shown that the three-stage router is nonblocking for one-to-one connections. This three stage topology has advantages over a single stage matrix having M inputs and N outputs, since as M and N increase, there are practical difficulties associated with constructing a switch having MxN crosspoints.
The conventional three-stage router having m+nxe2x88x921 second stage modules is not nonblocking with respect to one-to-many, i.e. broadcast, connections. It has been suggested that the three-stage router could be rendered nonblocking with respect to broadcast connections if it had one additional second stage router module, so that there were m+n second stage router modules. It would, of course, then be necessary to increase by one the number of outputs of each first stage module and to increase by one the number of inputs of each third stage module.
It has also been suggested that even though a three-stage router having m+n second stage router modules is nonblocking with respect to broadcast connections, i.e. the router can make any desired set of broadcast connections, each from one input terminal to one or more output terminals, provided only that there is no input terminal or output terminal common to two or more connections, it might nevertheless be necessary to repath an existing connection in order to make a new connection. The need to repath an existing connection may be subject to disadvantage. Suppose, for example, that the three-stage router is being used for routing digital signals that do not change state except at the beginning or end of a bit cell having a duration of 200 ns and that the router is configured to connect the ith input terminal to the jth output terminal over a path having a delay of 100 ns. After the router has settled, bits would be received at the jth output terminal at intervals of 200 ns, determined by the duration of the bit cell and not by the path delay through the router. Suppose further that the connection from the ith input terminal to the jth output terminal is to be repathed, and that the new connection will have a delay of 150 ns. Immediately after the router has been reconfigured, there would be an interval of 50 ns during which the state of the jth output terminal would be uncertain and then the bits would resume at 200 ns intervals. The interval of 50 ns during which the output signal is uncertain could result in a downstream machine that receives the signal from the router losing synchronization with the signal or otherwise behaving in an unexpected way. Consequently, a signal that is repathed behaves as though it were switched even though the user of the router would not have anticipated this.
In accordance with a first aspect of the invention there is provided a signal router having M input terminals and N output terminals and comprising an input router stage having M inputs connected respectively to the M input terminals of the router and composed of M/m router modules each having m inputs, p outputs and a first switch means for selectively connecting any one of the m inputs to any one of the p outputs, and an intermediate router stage composed of p router modules each having M/m inputs and N/n outputs and a second switch means for selectively connecting any one of the M/m inputs to any one of the N/n outputs, an output router stage composed of N/n router modules each having p inputs and n outputs and a third switch means for selectively connecting any one of the p inputs to any one of the n outputs, p*(M/m) input stage clocked storage elements connected respectively between the outputs of the router modules of the input router stage and the inputs of the router modules of the intermediate router stage, the input stage clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the input router stage (1 less than =i less than =p; 1 less than =j less than =M/m) and hold the signal level at the jth input of the pth router module of the intermediate router stage until a subsequent trigger event of the clock signal, p*N/n intermediate stage clocked storage elements connected respectively between the outputs of the router modules of the intermediate router stage and the inputs of the router modules of the output router stage, the intermediate stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the kth output of the lth router module of the second router stage (1 less than =k less than =N/n; 1 less than =1 less than =p) and hold the signal level at the lth input of the kth router module of the output router stage until a subsequent trigger event of the clock signal, and N output stage clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the output stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the third router stage (1 less than =u less than =n; 1 less than =v less than =N/n) and hold the signal level at the (n*v+u)th output terminal of the router until a subsequent trigger event of the clock signal.
In accordance with a second aspect of the invention there is provided a signal router comprising a first router stage composed of M/m router modules each having m inputs and m+n outputs and a first switch means for selectively connecting any one of the m inputs to any selected set of the m+n outputs, a second router stage composed of m+n router modules each having M/m inputs and N/n outputs and a second switch means for selectively connecting one of the M/m inputs to any selected set of the N/n outputs, a third router stage composed of N/n router modules each having m+n inputs and n outputs and a third switch means for selectively connecting any one of the m+n inputs to any selected set of the n outputs, (n+m)*(M/m) first clocked storage elements connected respectively between the outputs of the router modules of the first router stage and the inputs of the router modules of the second router stage, the first clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the first router stage (1 less than =i less than =m; 1 less than =j less than =M/m) and hold the signal level at the jth input of the ith router module of the second router stage until a subsequent trigger event of said clock signal, (n+m)*(N/n) second clocked storage elements connected respectively between the outputs of the router modules of the second router stage and the inputs of the router modules of the third router stage, the second clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the kth output of the lth router module of the second router stage (1 less than =k less than =N/n; 1 less than =1 less than =m+n) and hold the signal level at the lth input of the kth router module of the third router stage until a subsequent trigger event of said clock signal, and N third clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the third clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the third router stage (1 less than =u less than =n; 1 less than =v less than =N/n) and hold the signal level at the (v*n+u)th output terminal of the router until a subsequent trigger event of said clock signal.
In accordance with a third aspect of the invention there is provided a signal router comprising a first router stage composed of M/m router modules each having m inputs and p outputs and a first switch means for selectively connecting any one of the m inputs to any selected set of the p outputs, a second router stage having p*M/m inputs associated respectively with the outputs of the router modules of the first router stage and also having q*N/n outputs and including a second switch means for selectively interconnecting the p*M/m inputs and the q*N/n outputs, a third router stage composed of N/n router modules each having p inputs and n outputs and a third switch means for selectively connecting any one of the p inputs to any selected set of the n outputs, the inputs of the router modules of the third router stage being associated respectively with the q*N/n outputs of the second router stage, p*(M/m) first clocked storage elements connected respectively between the outputs of the router modules of the first router stage and the respectively associated inputs of the second router stage, the first clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the first router stage (1 less than =i less than =m; 1 less than =j less than =M/m) and hold the signal level at the associated input of the second router stage until a subsequent trigger event of the clock signal, p*(N/n) second clocked storage elements connected respectively between the outputs of the second router stage and the respectively associated inputs of the router modules of the third router stage, the second clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at an output of the second router stage and hold the signal level at the associated input of a router module of the third router stage until a subsequent trigger event of the clock signal, and N third clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the third clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the first router stage (1 less than =u less than =n; 1 less than =v less than =N/n) and hold the signal level at the (n*v+u)th output terminal of the router until a subsequent trigger event of the clock signal.